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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
FEATURES:
* * * * A and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in the SOIC and QSOP packages
IDT74FCT823AT/CT
DESCRIPTION:
The FCT823T series is built using an advanced dual metal CMOS technology. The FCT823T series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT823T is a 9-bit wide buffered register with Clock Enable (EN) and Clear (CLR) - ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823T high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for lowcapacitance bus loading in high-impedance state.
* * * *
FUNCTIONAL BLOCK DIAGRAM
D0 EN DN
CLR D CL Q D CL Q
CP Q
CP Q
CP
OE Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
YN
INDUSTRIAL TEMPERATURE RANGE
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JUNE 2006
DSC-5487/4
(c) 2006 Integrated Device Technology, Inc.
IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SOIC/ QSOP TOP VIEW
PIN DESCRIPTION
Pin Names Dx CLR I/O I I Description D Flip-Flop Data Inputs When the clear input is LOW and OE is LOW, the Qx outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-to-HIGH transition. Register 3-State Outputs Clock Enable. When the clock enable is LOW, data on the Dx output is transferred to the Qx output on the LOW-to-HIGH transition. When the clock enable is HIGH, the Qx outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE is HIGH, the Yx outputs are in the high-impedance state. When the OE is LOW, the TRUE register data is present at the Yx outputs.
FUNCTION TABLE(1)
OE H H H L H L H H L L CLR H H L L H H H H H H Inputs EN L L X X H H L L L L Dx L H X X X X L H L H CP X X X X Internal/ Outputs Qx Yx L Z H Z L Z L L NC Z NC NC L Z H Z L L H H Function High Z Clear Hold Load
CP Yx EN
I O I
OE
I
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level NC = No Change = LOW-to-HIGH Transition Z = High Impedance
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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA -- Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current(4) Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VI = 2.7V VI = 0.5V VI = 2.7V VI = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH VOL IOS IOFF Parameter Output HIGH Voltage Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Max., VO = GND(3) Test Conditions(1) IOH = -8mA IOH = -15mA IOL = 48mA Min. 2.4 2 -- -60 -- Typ.(2) 3.3 3 0.3 -120 -- Max. -- -- 0.5 -225 1 Unit V V mA A
VCC = 0V, VIN or VO 4.5V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND One Bit Toggling at fi = 5MHz VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND Eight Bits Toggling at fi = 2.5MHz VIN = 3.4V VIN = GND -- 6 16.3(5) VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
1.5
3.5
mA
VIN = 3.4V VIN = GND VIN = VCC VIN = GND
--
2
5.5
--
3.8
7.3(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT823AT Symbol tPLH tPHL Parameter Propagation Delay CP to Yx (OE = LOW) Condition(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 tSU tH tSU tH tPHL tREM tW tW tPZH tPZL Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP Set-up Time HIGH or LOW EN to CP Hold Time HIGH or LOW EN to CP Propagation Delay, CLR to Yx Recovery Time CLR to CP Clock Pulse Width HIGH or LOW CLR Pulse Width LOW Output Enable Time OE to Yx CL = 50pF RL = 500 CL = 300pF(4) RL = 500 tPHZ tPLZ Output Disable Time OE to Yx CL = 5pF(4) RL = 500 CL = 50pF RL = 500
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. This condition is guaranteed but not tested.
FCT823CT Max. 10 20 -- -- -- -- 14 -- -- -- 12 23 7 8 Min.(2) 1.5 1.5 3 1.5 3 0 1.5 6 6 6 1.5 1.5 1.5 1.5 Max. 6 12.5 -- -- -- -- 8 -- -- -- 7 12.5 6 6.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min.(2) 1.5 1.5 4 2 4 2 1.5 6 7 6 1.5 1.5 1.5 1.5
CL = 50pF RL = 500
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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500W VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
50pF CL
500W
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Octal Link Octal Link
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ
DISABLE 3V 1.5V 0V 3.5V 0.3V 0.3V VOL VOH 0V
Octal Link
tPLZ
Octal Link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXX XX FCT Temp. Range Device Type X Package
SO SOG Q QG
Small Outline IC SOIC - Green Quarter-size Small Outline Package QSOP - Green
823AT 823CT
Bus Interface Register
74
- 40C to +85C
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for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
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